The present invention relates to memory devices usable in data processing systems, and more particularly to an apparatus for enhancing the operation of random access memory (RAM) devices.
Data processing systems having a main memory made up of a plurality of RAM memory devices arranged into blocks are known. Each block is selected by select lines such that only the block of interest is selected during a memory operation.
Also known are memory refresh schemes in which the memory row of the RAM devices is refreshed with each memory read, with each memory access, and automatically at the end of a set period of time. Many RAM devices require external means for generating and multiplexing row addresses for refreshing. Some RAM devices incorporate a row address counter and a multiplexer for refreshing, but require an external refresh timing signal. Refresh counters which generate the row address to be refreshed during each time interval are also known.
RAM devices which operate in a "page mode" in which sequential accesses to the device may be made in the same row are also known. In the page mode operation, the original row address strobed into the device at the beginning of the page mode operation is held in the device and only new column addresses are strobed into the device, allowing for faster operation.
U.S. Patents of interest are: 4,292,676 issued Sept. 29, 1981 to Heniz; 4,296,480 issued Oct. 20, 1981 to Eaton, Jr. et al.; 4,328,566 issued May 4, 1982 to Thaler; 4,333,167 issued Jan. 1, 1982 to McElroy; 4,347,589 issued Aug. 31, 1982 to Proebsting; 4,415,992 issued Nov. 15 1983 to Adlhock; and 4,486,860 issued Dec. 4, 1984 to Takemae et al.